Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FinFET is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along the vertical sidewalls of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
FinFET ICs have traditionally been fabricated using semiconductor on insulator (SOI) substrates. There are significant advantages, however, to fabricating FinFET ICs on a bulk semiconductor substrate, including the significantly lower cost and higher crystalline quality of a bulk semiconductor substrate compared to a SOI substrate. Some problems that are easily solved when using SOI substrates must be addressed when fabricating FinFET ICs on a bulk semiconductor substrate. One of those problems involves isolation between adjacent fins and between adjacent active areas. When using a SOI substrate, isolation between fins is achieved by etching away all of the semiconductor material between the fins, leaving the fins extending upwardly from the underlying insulating material. Fabrication of FinFET ICs on bulk semiconductor substrates, however, requires two different types of insulator filled trenches. Shallow insulator filled trenches provide isolation between fins, and deep insulator filled trenches provide isolation between active areas. The shallow trenches are usually narrow and high density while the deep trenches tend to be wide and low density. The combination of the two types of isolation trenches, one shallow, narrow and dense, the other deep, wide, and low density, creates problems with planarization and etch processing steps. “Dishing” tends to occur over and adjacent to the low density regions during etch or planarization. The dishing leads to non-planar surfaces and to variation in fin height. The variation in fin height, in turn, results in non-uniformity of channel width and FinFET characteristics.
Accordingly, it is desirable to provide methods for fabricating FinFET integrated circuits that provide the necessary isolation uniformly across a semiconductor substrate. In addition, it is desirable to provide methods for fabricating FinFET ICs in bulk semiconductor substrates that avoid insulator non-uniformity. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.